Tuning tunnel barrier in Si3N4-based resistive memory embedding SiO2 for low-power and high-density cross-point array applications

Sungjun Kim; Byung Gook Park

doi:10.1016/j.jallcom.2015.12.107

Tuning tunnel barrier in Si₃N₄-based resistive memory embedding SiO₂ for low-power and high-density cross-point array applications

Sungjun Kim
, Byung Gook Park

Department of Electronics & Electrical Engineering

Seoul National University

Research output: Contribution to journal › Article › peer-review

29 Scopus citations

Abstract

In this paper, nonlinear and low-power resistive switching characteristics of Si₃N₄-based RRAM embedding SiO₂ tunnel barrier (TB) with full compatibility to conventional Si CMOS processing have been extensively studied to solve crosstalk issue in a cross-point structure. It is found that the nonlinear characteristics of a simple metal-insulator-insulator-silicon (MIIS) structure are mainly attributed to two different tunneling mechanisms in the SiO₂ layer. Furthermore, we offer an optimized solution by modulating compliance current (I_CC), read voltage (V_READ), and TB thickness for higher selectivity. Low current operation tuned by I_CC, V_READ, and TB thickness is essential to achieve higher selectivity for low-power and high-density cross-point array applications.

Original language	English
Pages (from-to)	256-261
Number of pages	6
Journal	Journal of Alloys and Compounds
Volume	663
DOIs	https://doi.org/10.1016/j.jallcom.2015.12.107
State	Published - 5 Apr 2016

Keywords

Resistive random-access memory (RRAM)
Silicon dioxide (SiO)
Silicon nitride (SiN)
Tunnel barrier

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10.1016/j.jallcom.2015.12.107

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title = "Tuning tunnel barrier in Si3N4-based resistive memory embedding SiO2 for low-power and high-density cross-point array applications",

abstract = "In this paper, nonlinear and low-power resistive switching characteristics of Si3N4-based RRAM embedding SiO2 tunnel barrier (TB) with full compatibility to conventional Si CMOS processing have been extensively studied to solve crosstalk issue in a cross-point structure. It is found that the nonlinear characteristics of a simple metal-insulator-insulator-silicon (MIIS) structure are mainly attributed to two different tunneling mechanisms in the SiO2 layer. Furthermore, we offer an optimized solution by modulating compliance current (ICC), read voltage (VREAD), and TB thickness for higher selectivity. Low current operation tuned by ICC, VREAD, and TB thickness is essential to achieve higher selectivity for low-power and high-density cross-point array applications.",

keywords = "Resistive random-access memory (RRAM), Silicon dioxide (SiO), Silicon nitride (SiN), Tunnel barrier",

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T1 - Tuning tunnel barrier in Si3N4-based resistive memory embedding SiO2 for low-power and high-density cross-point array applications

AU - Kim, Sungjun

AU - Park, Byung Gook

PY - 2016/4/5

Y1 - 2016/4/5

N2 - In this paper, nonlinear and low-power resistive switching characteristics of Si3N4-based RRAM embedding SiO2 tunnel barrier (TB) with full compatibility to conventional Si CMOS processing have been extensively studied to solve crosstalk issue in a cross-point structure. It is found that the nonlinear characteristics of a simple metal-insulator-insulator-silicon (MIIS) structure are mainly attributed to two different tunneling mechanisms in the SiO2 layer. Furthermore, we offer an optimized solution by modulating compliance current (ICC), read voltage (VREAD), and TB thickness for higher selectivity. Low current operation tuned by ICC, VREAD, and TB thickness is essential to achieve higher selectivity for low-power and high-density cross-point array applications.

AB - In this paper, nonlinear and low-power resistive switching characteristics of Si3N4-based RRAM embedding SiO2 tunnel barrier (TB) with full compatibility to conventional Si CMOS processing have been extensively studied to solve crosstalk issue in a cross-point structure. It is found that the nonlinear characteristics of a simple metal-insulator-insulator-silicon (MIIS) structure are mainly attributed to two different tunneling mechanisms in the SiO2 layer. Furthermore, we offer an optimized solution by modulating compliance current (ICC), read voltage (VREAD), and TB thickness for higher selectivity. Low current operation tuned by ICC, VREAD, and TB thickness is essential to achieve higher selectivity for low-power and high-density cross-point array applications.

KW - Resistive random-access memory (RRAM)

KW - Silicon dioxide (SiO)

KW - Silicon nitride (SiN)

KW - Tunnel barrier

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DO - 10.1016/j.jallcom.2015.12.107

M3 - Article

AN - SCOPUS:84952684555

SN - 0925-8388

VL - 663

SP - 256

EP - 261

JO - Journal of Alloys and Compounds

JF - Journal of Alloys and Compounds

ER -

Tuning tunnel barrier in Si₃N₄-based resistive memory embedding SiO₂ for low-power and high-density cross-point array applications

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Keywords

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