@inproceedings{8ee1f32205074c60a66ba86c5c133f83,
title = "Two-step ADC with Self-Successive Doubling Algorithm for High-Speed CIS",
abstract = "This paper presents a high-speed CMOS image sensor (CIS) using a two-step analog-to-digital converter (ADC) that applies the self-successive doubling (SSD) algorithm. The proposed readout circuit uses a successive approximation register (SAR) ADC to implement a high-speed CIS and addresses the area requirements of the SAR ADC by employing an SSD circuit. The SSD circuit has a structure similar to conventional analog correlated double sampling (CDS) circuits, which simultaneously perform CDS and ADC operations. The proposed high-speed two-step ADC uses SSD logic for MSB and SAR ADC for LSB, thereby reducing the capacitance area by about 96.8\% compared to a conventional 12-bit SAR-ADC. The proposed circuit is fabricated using a 180 nm process, with a total power consumption of 7.54 mW and a frame rate of 1190 fps.",
keywords = "CMOS Image sensor, Pipeline ADC, SAR ADC, Two-step ADC",
author = "Kyungmin Lee and Minkyu Song and Kim, \{Soo Youn\}",
note = "Publisher Copyright: {\textcopyright} 2025 IEEE.; 2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025 ; Conference date: 25-05-2025 Through 28-05-2025",
year = "2025",
doi = "10.1109/ISCAS56072.2025.11044104",
language = "English",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings",
address = "United States",
}