Two-step Classification Neuron Circuits for Low-power and High-integration SNN Systems

This paper presents low-power and high-integration spiking neural network (SNN) systems with proposed two-step classification neuron circuits. When the first classification based on the main-post spike is challenging to infer due to the identical number of output spikes, the second layer post generator processes the final inference, resulting in improved accuracy. Furthermore, by distributing membrane capacitance owing to the proposed two-step classification, the area and power consumption of neuron circuits can be reduced. The proposed neuron circuits in an SNN system are fabricated using a 28nm CMOS process and demonstrated with a 144-25-10 Modified National Institute of Standards and Technology (MNIST) classification network trained with MATLAB®. Compared to the conventional classification method, the neuron power consumption and membrane capacitor area were reduced by 60% and 70%, respectively. Furthermore, we observed that the inference accuracy increased from 94.41% to 95.41%.