Abstract
Interpolation plays a key role in the fractional motion estimation (FME) of video encoders. A hardware implementation of a FME interpolator is presented for high efficiency video coding. The proposed interpolator processes each 8 × 8 block in a pipelined manner with efficiently shared finite impulse response filters to improve the performance while reducing gate counts. Implementation results show that the proposed design leads to fewer execution cycles with a small silicon area compared with conventional designs.
Original language | English |
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Pages (from-to) | 1163-1165 |
Number of pages | 3 |
Journal | Electronics Letters |
Volume | 51 |
Issue number | 15 |
DOIs | |
State | Published - 23 Jul 2015 |